1kHz Real-Time Robot Control System Monitoring Architecture
Design a monitoring architecture that safely collects, stores, and visualizes performance data from EtherCAT-based 1kHz real-time control loops. Maintain RT determinism while capturing debugging data using Lock-free SPSC Queues and ROS2 topic layering.
How Robots Understand 3D Space: Voxels and SDF
Explains Voxel, SDF, TSDF, and ESDF technologies that robots use to represent and understand 3D environments. Covers differences from Point Clouds and practical applications in robot path planning and surface reconstruction.
Improving Robot Position Tracking Accuracy: Acceleration Feedforward Optimization Journey
We share the process of optimizing acceleration feedforward control for a 6-axis robot arm. By using planner acceleration + LPF instead of numerical differentiation, we achieved 21.2% improvement in position RMSE and torque stability simultaneously.
Lock-free vs Mutex: Robot Control System IPC Performance Benchmark
The factor determining IPC performance in robot control systems is the synchronization mechanism, not process boundaries. We share a case study achieving 100x improvement from 78-103us with Mutex to 0.74-0.82us with Lock-free.
MotoROS2 Point Queue Proxy Server - Breaking the 200-Point Limit
Learn how to overcome MotoROS2's 200-point trajectory limitation and BUSY response issues on Yaskawa industrial robots through a Proxy Server architecture design and implementation.
Precision Robot Calibration Using Touch Probe and Kabsch Algorithm
A practical guide to achieving sub-0.5mm Sim-to-Real calibration by combining Touch Probe and Kabsch Algorithm to overcome the limitations of vision-based approaches.
Validating Robot Friction Compensation Effects
We validate the effects of friction compensation and acceleration feedforward on a 6-axis collaborative robot through 160 runs of 2x2 experiments. Friction coefficients were tuned using an AI agent (ralph-loop), and validation experiments were conducted with automated scripts. Friction compensation alone achieved 36% improvement (Cohen's d=1.49), accounting for 93% of total improvement.
What is the Real Cost of std::memory_order on ARM64? - Jetson Orin Benchmark
We measured whether atomic memory ordering could be a performance bottleneck in a 1kHz RT loop on Jetson Orin (Cortex-A78AE). On AArch64, the cost of seq_cst is virtually identical to release/acquire, and the total cost of 25 atomic operations is less than 0.01% of the 1ms budget.