실시간 시스템, 커널, IPC, 메모리 관련 기술과 실무 경험을 공유합니다.
We measured whether atomic memory ordering could be a performance bottleneck in a 1kHz RT loop on Jetson Orin (Cortex-A78AE). On AArch64, the cost of seq_cst is virtually identical to release/acquire, and the total cost of 25 atomic operations is less than 0.01% of the 1ms budget.
The factor determining IPC performance in robot control systems is the synchronization mechanism, not process boundaries. We share a case study achieving 100x improvement from 78-103us with Mutex to 0.74-0.82us with Lock-free.
Design a monitoring architecture that safely collects, stores, and visualizes performance data from EtherCAT-based 1kHz real-time control loops. Maintain RT determinism while capturing debugging data using Lock-free SPSC Queues and ROS2 topic layering.
We validate with measured data whether PREEMPT_RT kernel and CPU isolation alone can enable 1kHz EtherCAT control on NVIDIA Jetson Orin. Under GPU, Storage, and EtherCAT load conditions, we achieved max latency below 20us.